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Formal Approach to Agent-Based Dynamic Reconfiguration in Networks-On-Chip

Sergey Ostroumov, Leonidas Tsiopoulos, Juha Plosila, Kaisa Sere, Formal Approach to Agent-Based Dynamic Reconfiguration in Networks-On-Chip. Journal of Systems Architecture 59(9), 709–728, 2013.

Abstract:

Many-core embedded system will integrate a large number of cores (several hundred) in order to meet the performance requirements of parallel applications. These cores can be simple processor cores, programmable processors, co-processors, accelerators, application-specific IPs, peripherals, memories, reconfigurable logic, and even analog blocks. As the number of cores integrated into a chip increases, the conventional on-chip communication becomes power and performance bottleneck in many-core embedded systems. Network-on-Chip (NoC) architectures have been emerged as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure in many-core embedded systems. NoC provides an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared with traditional infrastructures.

The purpose of this Special Issue is to collect timely and selected research contributions to network-based many-core embedded systems. In particular, the main focus covers important areas of NoC and related design and implementation topics for efficient interconnection of cores. In what follows, we will give a brief overview of the accepted papers of this special issue based on their topics.

BibTeX entry:

@ARTICLE{ejDaLiMoIn13a,
  title = {Formal Approach to Agent-Based Dynamic Reconfiguration in Networks-On-Chip},
  author = {Ostroumov, Sergey and Tsiopoulos, Leonidas and Plosila, Juha and Sere, Kaisa},
  journal = {Journal of Systems Architecture},
  volume = {59},
  number = {9},
  publisher = {Elsevier},
  pages = {709–728},
  year = {2013},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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