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Emerging On-Chip Networks and Architectures

Terrence Mak, Maurizio Palesi, Masoud Daneshtalab (Eds.), Emerging On-Chip Networks and Architectures. IET Computers and Digital Techniques 7(6), 2013.

Abstract:

By entering into the ultra deep sub-micron era, the role played
by the on-chip communication system is getting more and
more critical. On-chip communication system represents
one of the most important elements that determines
the overall performance, cost, reliability, and energy
consumption of a modern multi-processor system-on-chip
(MPSoC). If the raw computation horsepower seems to be
unlimited thanks to the ability of instancing more and more
cores in a single silicon die, scalability issues, due to the
need of making ef
fi
cient and reliable the communication
between the increasing number of cores, becomes the real problem. The Network-on-Chip (NoC) paradigm is now considered as the most viable solution for designing on-chip communication systems able to tackle with the above issues. This Special Issue aims to provide a forum for researchers to present innovative ideas and solutions related to design and implementation of networks-on-chip. Particularly, this Special Issue focuses on issues related to design, analysis and new communication approach of on-chip and on-system networks. In what follows, we will give a brief overview of the accepted papers of this Special Issue based on their topics.

BibTeX entry:

@PERIODICAL{ejMaPaDa13a,
  title = {Emerging On-Chip Networks and Architectures},
  journal = {IET Computers and Digital Techniques},
  volume = {7},
  number = {6},
  editor = {Mak, Terrence and Palesi, Maurizio and Daneshtalab, Masoud},
  publisher = {Institution of Engineering and Technology},
  year = {2013},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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