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Cost of Sparse Mesh Layouts Supporting Throughput Computing

Martti Forsell, Ville Leppänen, Martti Penttonen, Cost of Sparse Mesh Layouts Supporting Throughput Computing. In: Paris Kitsos (Ed.), Proceedings, 14th Euromicro Conference on Digital System Design, DSD'2011, 316-323, IEEE Computer Society, 2011.

Abstract:

The purpose of this paper is to estimate the cost of utilizing
underpopulated, or sparse, networks on chip (NOC) for chip
multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes
are sources and sinks whereas the rest are simple intermediate nodes
increasing communication bandwidth. Compared to dense NOCs, where all
nodes can be sources and sinks of communication, the underpopulated
NOCs can be scaled so that any degree of communication frequency of
nodes can be supported. The drawback of underpopulated NOCs is larger
network area and bigger logical diameter. GPGPU-style stream-based or
high-throughput CMPs can be used to hide the effect of longer
latencies. In this paper, we present layouts for mesh-based
underpopulated networks, calculate their wirelength distributions and
the overall area. Moreover, we present energy consumption calculations
for such networks, and show that while the network part of a CMP
system based on underpopulated NOCs can play a major role when
considering the chip area and energy consumption, it can be pushed
down by increasing the number of dimensions and using meshes instead
of tori. We also compare various multidimensional sparse mesh- layouts
and conclude the 3-dimensional and 4-dimensional sparse meshes to be
the most attractive ones for throughput computing.

BibTeX entry:

@INPROCEEDINGS{iFoLePe11a,
  title = {Cost of Sparse Mesh Layouts Supporting Throughput Computing},
  booktitle = {Proceedings, 14th Euromicro Conference on Digital System Design, DSD'2011},
  author = {Forsell, Martti and Leppänen, Ville and Penttonen, Martti},
  editor = {Kitsos, Paris},
  publisher = {IEEE Computer Society},
  pages = {316-323},
  year = {2011},
  keywords = {Network on chip, sparse networks, layouts, comparison, throughput computing},
}

Belongs to TUCS Research Unit(s): Algorithmics and Computational Intelligence Group (ACI)

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