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Design of a High-Performance and Secure Networks-on-Chip

Khalid Latif, Amir-mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen, Design of a High-Performance and Secure Networks-on-Chip. In: Radu Dobrin (Ed.), International Workshop on Dependable and Secure Industrial and Embedded Systems (WORDS’11), 1-6, Mälardalen University, Sweden, 2011.

Abstract:

A novel PVS-NoC architecture aiming for better performance and overhead tradeoff is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among multiple inputs, which provides the performance advantage as conventional VC-based router with minimized overhead. We reason theoretically and demonstrate quantitatively the benefits of proposed architecture for various traffic patterns. Extensive experiments with synthetic benchmarks show significant improvement in system throughput as compared to the typical VC based NoC architectures.

BibTeX entry:

@INPROCEEDINGS{iLaRaSeTe11a,
  title = {Design of a High-Performance and Secure Networks-on-Chip},
  booktitle = {International Workshop on Dependable and Secure Industrial and Embedded Systems (WORDS’11)},
  author = {Latif, Khalid and Rahmani, Amir-mohammad and Seceleanu, Tiberiu and Tenhunen, Hannu},
  editor = {Dobrin, Radu},
  publisher = {Mälardalen University, Sweden},
  pages = {1-6},
  year = {2011},
  keywords = {Virtual Channel Sharing, Networks-on-Chip (NoC), Resource Utilization},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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