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A RISC-Based Moving Tiny Threads Architecture

Ville Leppänen, Jari-matti Mäkelä, Martti Forsell, A RISC-Based Moving Tiny Threads Architecture. In: Hamid Arabnia (Ed.), Proceedings of 2011 Conference on Parallel and Distributed Processing Techniques and Appliations, PDPTA'11, II, 485-491, CSREA Press, 2011.

Abstract:

We describe a RISC-based architecture for moving tiny light-weight
threads instead of data in the multicore context. We assume the
architecture to consist of homogeneous cores that are connected with
an on-chip network. A sparse 3D torus is considered as a network
delivering enough bandwidth. Besides rather ordinary ALU
capabilities, each core maintains a rather large set of threads, and
has separate memory and instruction caches. For the data cache, we
avoid coherence problems by partitioning the memory and assuming that
a portion of the main memory can be accessed only via one specific
data cache. Consequently, we need to move light-weight
hardware-supported threads between the cores in the on-chip network.

Compared to approaches where all memory locations are accessible via
each cache, we avoid coherence problems and do less loads to caches.
The price is an additional network between the cores and possible
inefficiencies due to moving threads between the cores. As the
threads in each core are used to hide memory access and thread moving
latencies, we characterize requirements for the amount of tiny threads.

BibTeX entry:

@INPROCEEDINGS{iLeM_Fo11a,
  title = {A RISC-Based Moving Tiny Threads Architecture},
  booktitle = {Proceedings of 2011 Conference on Parallel and Distributed Processing Techniques and Appliations, PDPTA'11},
  author = {Leppänen, Ville and Mäkelä, Jari-matti and Forsell, Martti},
  volume = {II},
  editor = {Arabnia, Hamid},
  publisher = {CSREA Press},
  pages = {485-491},
  year = {2011},
  keywords = {Moving threads, architecture, RISC-based},
}

Belongs to TUCS Research Unit(s): Algorithmics and Computational Intelligence Group (ACI)

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