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Mapping the DVB Physical Layer onto SDR-enabled Protocol Processor Hardware

Muhammad Imran Anwar, Seppo Virtanen, Mapping the DVB Physical Layer onto SDR-enabled Protocol Processor Hardware. In: Proceedings of the 23rd IEEE Norchip Conference, IEEE Circuits and Systems Society, 2005.

Abstract:

We present the design and implementation of configurable
protocol processor hardware modules for SDR
applications. We approach the problem by mapping
digital television functionality onto our existing TTA protocol
processor architecture. The implemented hardware
modules include Symbol, Bit and Convolutional Deinterleavers,
Depuncturer and Demapper. The hardware
was synthesized using 0.18 micron technology and verified
with VHDL simulations. The resulting processor area
was 2.2 sq-mm which is almost three times the area we
have previously obtained for a complex network layer
processor with identical data transport capacity.

BibTeX entry:

@INPROCEEDINGS{inpAnVi05a,
  title = {Mapping the DVB Physical Layer onto SDR-enabled Protocol Processor Hardware},
  booktitle = {Proceedings of the 23rd IEEE Norchip Conference},
  author = {Anwar, Muhammad Imran and Virtanen, Seppo},
  publisher = {IEEE Circuits and Systems Society},
  year = {2005},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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