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Low-Latency Hardware Architecture for Cipher-Based Message Authentication Code

Imed Ben Dhaou, Tuan Nguyen Gia, Pasi Liljeberg, Hannu Tenhunen, Low-Latency Hardware Architecture for Cipher-Based Message Authentication Code. In: Pamela Abshire, Ralph Etienne-Cummings (Eds.), Low-Latency Hardware Architecture for Cipher-Based Message Authentication Code, 1–4, IEEE, 2017.

Abstract:

Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbp

BibTeX entry:

@INPROCEEDINGS{inpBeNgLiTe17a,
  title = {Low-Latency Hardware Architecture for Cipher-Based Message Authentication Code},
  booktitle = {Low-Latency Hardware Architecture for Cipher-Based Message Authentication Code},
  author = {Ben Dhaou, Imed and Nguyen Gia, Tuan and Liljeberg, Pasi and Tenhunen, Hannu},
  editor = {Abshire, Pamela and Etienne-Cummings, Ralph},
  publisher = {IEEE},
  pages = {1–4},
  year = {2017},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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