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Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Sudeep Kanur, Georgios Georgakarakos, Antti Siirilä, Jérémie Lagravière, Kristian Nybom, Sébastien Lafond, Johan Lilius, Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. In: Waleed W. Smari (Ed.), High Performance Computing and Simulation (HPCS), 2013 International Conference on, 202–206, IEEE, 2013.

http://dx.doi.org/10.1109/HPCSim.2013.6641414

Abstract:

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

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BibTeX entry:

@INPROCEEDINGS{inpKaGeSiLaNyLaLi13a,
  title = {Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study},
  booktitle = {High Performance Computing and Simulation (HPCS), 2013 International Conference on},
  author = {Kanur, Sudeep and Georgakarakos, Georgios and Siirilä, Antti and Lagravière, Jérémie and Nybom, Kristian and Lafond, Sébastien and Lilius, Johan},
  editor = {Smari, Waleed W.},
  publisher = {IEEE},
  pages = {202–206},
  year = {2013},
}

Belongs to TUCS Research Unit(s): Embedded Systems Laboratory (ESLAB)

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