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A Cluster-Based Core Protection Technique for Networks-on-Chip

Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Pasi Liljeberg, Hannu Tenhunen, A Cluster-Based Core Protection Technique for Networks-on-Chip. In: Xiaoying Bai, Fevzi Belli, Elisa Bertino, Carl K. Chang, Atilla Elçi, Cristina Seceleanu, Haihua Xie, Mohammad Zulkernine (Eds.), 36th Annual IEEE Computer Software and Applications Conference (COMPSAC), 360–361, IEEE Computer Society, 2012.

Abstract:

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead.

BibTeX entry:

@INPROCEEDINGS{inpLaRaSeLiTe12a,
  title = {A Cluster-Based Core Protection Technique for Networks-on-Chip},
  booktitle = {36th Annual IEEE Computer Software and Applications Conference (COMPSAC)},
  author = {Latif, Khalid and Rahmani, Amir-Mohammad and Seceleanu, Tiberiu and Liljeberg, Pasi and Tenhunen, Hannu},
  editor = {Bai, Xiaoying and Belli, Fevzi and Bertino, Elisa and Chang, Carl K. and Elçi, Atilla and Seceleanu, Cristina and Xie, Haihua and Zulkernine, Mohammad},
  publisher = {IEEE Computer Society},
  pages = {360–361},
  year = {2012},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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