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Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip

Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip. In: Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net 2007), 5 pages, 2007.

Abstract:

The amount of errors in future nanoscale technologies is expected to increase dramatically when compared to technologies that have line width larger than 90 nm. In nanoscale CMOS circuits fault tolerance is one of the most important design constraints to sustain system reliability at an
acceptable level. We analyze dierent error correcting coding methods for on-chip communication networks of future nanoscale multiprocessor systems. The implemented communication circuits are compared in terms of error correction capability, circuit area and power consumption. In addition,
performance of implemented systems is evaluated under different error scenarios by taking into account variable number of single bit errors, burst errors, and their combinations.

BibTeX entry:

@INPROCEEDINGS{inpLeLiPl07b,
  title = {Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip},
  booktitle = {Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net 2007)},
  author = {Lehtonen, Teijo and Liljeberg, Pasi and Plosila, Juha},
  pages = {5 pages},
  year = {2007},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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