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Fault Tolerance Analysis of NoC Architectures

Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Fault Tolerance Analysis of NoC Architectures. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2007), 361-364, 2007.

Abstract:

We present an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate.

BibTeX entry:

@INPROCEEDINGS{inpLeLiPl07c,
  title = {Fault Tolerance Analysis of NoC Architectures},
  booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2007)},
  author = {Lehtonen, Teijo and Liljeberg, Pasi and Plosila, Juha},
  pages = {361-364},
  year = {2007},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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