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On-chip Debug for an Asynchronous Java Accelerator

Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere, On-chip Debug for an Asynchronous Java Accelerator. In: Proceedings of the 6th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005), IEEE Computer Society Press, 2005.

Abstract:

The solution to debug a problem in a deeply embedded system is to integrate the debug and communication module inside the chip. In this paper, we propose an on-chip in-circuit emulation (ICE) architecture for debugging an asynchronous Java accelerator core which can be integrated with any existing processor and operating system. The operation of this ICE module and the debug strategy of the Java accelerator are specifically designed for asynchronous implementation. They not only facilitate the system development but also provide a manufacture test method for asynchronous chips.

BibTeX entry:

@INPROCEEDINGS{inpLiPlYaSe05a,
  title = {On-chip Debug for an Asynchronous Java Accelerator},
  booktitle = {Proceedings of the 6th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005)},
  author = {Liang, Zheng and Plosila, Juha and Yan, Lu and Sere, Kaisa},
  publisher = {IEEE Computer Society Press},
  year = {2005},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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