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RISC-Based Moving Threads Multicore Architecture

Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell, RISC-Based Moving Threads Multicore Architecture. In: Boris Rachev, Angel Smrikarov (Eds.), Proceedings of 12th International Conference on Computer Systems and Technologies, CompSysTech'11, ACM ICPS 578, 51-56, ACM Press, 2011.

Abstract:

In this paper, we describe the architectural output of our 'Moving
threads realization study' (MOTH) project, which is a RISC-based
multicore architecture framework. Each fraction of the memory can be
accessed only via a certain core, via its cache memory. This
approach leads to moving light-weight threads but at the same time
provides strong memory coherence as no main memory location is
replicated to several caches. We describe the overall multicore
architecture, but special emphasis is put on describing the
functionality of individual RISC-based cores.

BibTeX entry:

@INPROCEEDINGS{inpM,
  title = {RISC-Based Moving Threads Multicore Architecture},
  booktitle = {Proceedings of 12th International Conference on Computer Systems and Technologies, CompSysTech'11},
  author = {Mäkelä, Jari-Matti and Leppänen, Ville and Forsell, Martti},
  volume = {578},
  series = {ACM ICPS},
  editor = {Rachev, Boris and Smrikarov, Angel},
  publisher = {ACM Press},
  pages = {51-56},
  year = {2011},
  keywords = {Moving threads, architecture, RISC-based, PRAM},
}

Belongs to TUCS Research Unit(s): Algorithmics and Computational Intelligence Group (ACI)

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