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MVTsim -- Software Simulator for Multicore on Chip Parallel Computer Architectures

Jari-Matti Mäkelä, Jani Paakkulainen, Ville Leppänen, MVTsim -- Software Simulator for Multicore on Chip Parallel Computer Architectures. In: Proceedings of International Conference on Computer Systems and Technologies, CompSysTech'09, 6 pages, 2009.

Abstract:

Designing a parallel computer architecture for the multicore on chip
environment involves a lot of architectural design issues. Actual
hardware design based on ASIC or for demonstrational purposes on FPGA
are very expensive methods to study the cost of various design
choices. Therefore, we have developed a software based simulator
MVTsim for multicore on chip parallel computers. Due to a special
theme of our research project, the simulator is oriented towards
supporting a very fine-grained moving threads approach.

We describe the general software architecture of the multicore on
chip simulator. In the simulator, we have given special emphasis for
the modular structure of the simulator, support for flexible
combining of different granularily levels of components, and
modelling relevant physical delay related properties. We demonstrate
our simulator by describing a RISC based configuration supporting the
moving threads approach, and give some initial results concerning
running actual programs with out simulator.

Files:

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BibTeX entry:

@INPROCEEDINGS{inpMaPaLe09a,
  title = {MVTsim -- Software Simulator for Multicore on Chip Parallel Computer Architectures},
  booktitle = {Proceedings of International Conference on Computer Systems and Technologies, CompSysTech'09},
  author = {Mäkelä, Jari-Matti and Paakkulainen, Jani and Leppänen, Ville},
  pages = {6 pages},
  year = {2009},
}

Belongs to TUCS Research Unit(s): Algorithmics and Computational Intelligence Group (ACI)

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