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A 1.2V 10bit 83MSps Pipeline ADC in 130nm CMOS

Hao Meng, Jia Sun, Ari Paasio, A 1.2V 10bit 83MSps Pipeline ADC in 130nm CMOS. In: Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics 2009 (PrimeAsia 2009), 177-180, IEEE Circuits and Systems Society, 2009.

Abstract:

A 1.2 V 10 bit 83 MS/s pipeline ADC implemented in 130 nm CMOS Technology is described. Emphasis was placed on noise analysis and capacitance optimization. Experience of operational amplifier, comparator and switch design were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33 LSB respectively, while SNDR is 57.7 dB.

BibTeX entry:

@INPROCEEDINGS{inpMeSuPa09a,
  title = {A 1.2V 10bit 83MSps Pipeline ADC in 130nm CMOS},
  booktitle = {Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics 2009 (PrimeAsia 2009)},
  author = {Meng, Hao and Sun, Jia and Paasio, Ari},
  publisher = {IEEE Circuits and Systems Society},
  pages = {177-180},
  year = {2009},
}

Belongs to TUCS Research Unit(s): Microelectronics

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