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Tuning a Protocol Processor Architecture Towards DSP Operations

Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho, Tuning a Protocol Processor Architecture Towards DSP Operations. In: Timo D. Hämäläinen (Ed.), SAMOS V (LNCS 3553), Lecture Notes in Computer Science 3553, 132–141, Springer-Verlag, 2005.

Abstract:

In this paper we present an experiment in enhancing our transport triggered protocol processor hardware platform to support DSP applications. Our focus is on integrating support for both application domains into a single processor without loss of performance in either domain. Such a processor could be taken advantage of in applications like Voice-over-IP communication using hand-held devices, where functionality is needed from both domains. As our first step in bridging the gap between the protocol processing and DSP domains we implement support for FIR filtering. We analyze four different architectural instances for implementing FIR filters according to their performance and bus utilisation. We were able to determine that protocol processing and DSP operations can be executed in parallel very efficiently. The implementations were verified with VHDL simulations and synthesis using 0.18 µm CMOS technology.

BibTeX entry:

@INPROCEEDINGS{inpPaViIs05a,
  title = {Tuning a Protocol Processor Architecture Towards DSP Operations},
  booktitle = {SAMOS V (LNCS 3553)},
  author = {Paakkulainen, Jani and Virtanen, Seppo and Isoaho, Jouni},
  volume = {3553},
  series = {Lecture Notes in Computer Science},
  editor = {Hämäläinen, Timo D.},
  publisher = {Springer-Verlag},
  pages = {132–141},
  year = {2005},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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