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Dual-NI Architectures for Fault Tolerant NoC

Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Dual-NI Architectures for Fault Tolerant NoC. In: Design, Automation and Test in Europe DATE Conference 2009, Digest of the Workshop on Diagnostic Services in Network-on-Chips, 2009.

Abstract:

Fault tolerance is an important aspect in designing Network-on-Chip (NoC) architectures for future multiprocessor systems. The paper presents dual network interface (dual-NI) NoC architectures for fault tolerant Network-on-Chip implementations. Network topologies and routing algorithms for dual-NI NoC architectures are presented and analyzed. The dual-NI architectures are based on connecting two network interfaces on each core (processing element). Additional network interfaces increase alternative routes to reach the cores and enter the network from cores in case of faulty links and routers. The aim is to improve fault tolerance on the topology level which means the delivery of packets to all the cores even when there are faulty links or routers in the network. The analysis shows that the fault tolerance of the NoC can be improved with dual network interface structures by decreasing the average hop counts and keeping the cores connectable even in the case of faults. The overhead of such structures is reasonable.

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BibTeX entry:

@INPROCEEDINGS{inpRaLeLiPl09a,
  title = {Dual-NI Architectures for Fault Tolerant NoC},
  booktitle = {Design, Automation and Test in Europe DATE Conference 2009, Digest of the Workshop on Diagnostic Services in Network-on-Chips},
  author = {Rantala, Ville and Lehtonen, Teijo and Liljeberg, Pasi and Plosila, Juha},
  year = {2009},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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