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Multi Network Interface Architectures for Fault Tolerant Network-on-Chip

Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Multi Network Interface Architectures for Fault Tolerant Network-on-Chip. In: International Symposium on Signals, Circuits and Systems (ISSCS '09), 145-148, IEEE, 2009.

Abstract:

The topology level fault tolerance of Network-on-Chip (NoC) can be improved with multi network interface (multi-NI) architectures. Multi-NI NoC architectures are based
on connecting at least two network interfaces on each core. The aim is to improve fault tolerance on the architectural level which means the delivery of packets even when there are faulty links or routers in the network. This paper presents architectures and algorithms for multi-NI NoCs. The analysis of the proposed architectures and algorithms shows that some of them improve the fault tolerance of NoC with a reasonable overhead by decreasing the average hop counts and keeping the
cores connectable even in the case of faults. With a multi-NI architecture the number of successfully delivered packets has been even doubled.

BibTeX entry:

@INPROCEEDINGS{inpRaLeLiPl09b,
  title = {Multi Network Interface Architectures for Fault Tolerant Network-on-Chip},
  booktitle = {International Symposium on Signals, Circuits and Systems (ISSCS '09)},
  author = {Rantala, Ville and Lehtonen, Teijo and Liljeberg, Pasi and Plosila, Juha},
  publisher = {IEEE},
  pages = {145-148},
  year = {2009},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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