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An Improved Hardware Acceleration Scheme for Java Method Calls

Tero Säntti, Joonas Tyystjärvi, Juha Plosila, An Improved Hardware Acceleration Scheme for Java Method Calls. In: Norchip 2010, 2010.

Abstract:

This paper presents a significantly improved strategy for accelerating the method calls in the REALJava co-processor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is implemented in an FPGA prototype. It allows measurements of real life performance increase, and validates the whole co-processor concept. The system is intended to be used in embedded environments, with limited CPU performance and memory available to the virtual machine. The co-processor is designed in a highly modular fashion, especially separating the communication from the actual core. This modularity of the design makes the co-processor more reusable and allows system level scalability. This work is a part of a project focusing on design of a hardware accelerated multicore Java Virtual Machine for embedded systems.

BibTeX entry:

@INPROCEEDINGS{inpSaTyPl10a,
  title = {An Improved Hardware Acceleration Scheme for Java Method Calls},
  booktitle = {Norchip 2010},
  author = {Säntti, Tero and Tyystjärvi, Joonas and Plosila, Juha},
  year = {2010},
}

Belongs to TUCS Research Unit(s): Other

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