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Arbitration for the Segmented Bus Architecture

Tiberiu Seceleanu, Stefan Stancescu, Arbitration for the Segmented Bus Architecture. In: IEEE International Semiconductor Conference (CAS 2004), 487-490, 2004.

Abstract:

In this study, we discuss arbitration aspects concerning a segmented bus
platform for SOC, at the level of the central arbiter unit. Placed
somewhere mid-way between the classical system bus and the network on chip
approaches, the segmented bus architecture provides certain performance
improvements in comparison with the first, while employing a much simpler
communication structure and algorithm than those thought for the second.
Our implementation strategy targets an FPGA technology. The result comes as
a parameterized arbitration and communication scheme for system on chip
designers.

BibTeX entry:

@INPROCEEDINGS{inpSeSt04a,
  title = {Arbitration for the Segmented Bus Architecture},
  booktitle = {IEEE International Semiconductor Conference (CAS 2004)},
  author = {Seceleanu, Tiberiu and Stancescu, Stefan},
  pages = {487-490},
  year = {2004},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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