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Self-Timed Approach for Reducing On-Chip Switching Noise

Johanna Tuominen, Pasi Liljeberg, Jouni Isoaho, Self-Timed Approach for Reducing On-Chip Switching Noise. In: IFIP WG 10.5 VLSI-SoC 2003, 19-24, 2003.

Abstract:

This paper describes a design methodology to reduce on-chip power
supply switching noise caused by current peaks related to
synchronous clock. In the proposed approach, a synchronously
operating system module is modified so that the clock based control
is replaced by a self-timed one. At the same time the external
interface is kept intact, without the need for synchronizers. The
method is applied to the path metric unit of the Viterbi decoder.
This reduces the peak current by 87 % compared to the fully
synchronous design. Furthermore, this approach allows the reduction
of the area devoted to the on-chip decoupling capacitance needed to
suppress power supply noise.

Files:

Abstract in PDF-format

Full publication in PDF-format

BibTeX entry:

@INPROCEEDINGS{inpTuLiIs03a,
  title = {Self-Timed Approach for Reducing On-Chip Switching Noise},
  booktitle = {IFIP WG 10.5 VLSI-SoC 2003},
  author = {Tuominen, Johanna and Liljeberg, Pasi and Isoaho, Jouni},
  pages = {19-24},
  year = {2003},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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