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Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation

Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen, Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. In: Proceedings of the 21st IEEE International Conference on VLSI Design, 228-234, IEEE, 2008.

Abstract:

In this paper, we model on-chip signaling over a bus consisting of
encoding, drivers, transmission lines, receivers and decoding. We
characterize the signaling circuitry as a function of its load capacitance.
The effective load capacitance seen by a driver is derived for the
decoupling method and distributed RLC transmission line models. The driver
delay and rise time corresponding to the derived effective capacitance are
used to derive the far-end voltage of a transmission line bus. The effects
of process variation are taken into account in the characterization of the
signaling circuitry and in the wire analysis. The overall delay variation
of the bus due to device and wire process variation is then calculated.
The model is verified by comparing it to HSPICE. We implement regular
voltage mode, level- encoded dual-rail and 1-of-4 signaling circuitry and
apply the derived model to analyze them. The implementation and analysis
are done in 45 nm technology.

BibTeX entry:

@INPROCEEDINGS{inpTuNiIsTe08a,
  title = {Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation},
  booktitle = {Proceedings of the 21st IEEE International Conference on VLSI Design},
  author = {Tuuna, Sampo and Nigussie, Ethiopia and Isoaho, Jouni and Tenhunen, Hannu},
  publisher = {IEEE},
  pages = {228-234},
  year = {2008},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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