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Comparative Study of Synthesis for Asynchronous and Synchronous Cache Controllers

Johanna Tuominen, Tero Säntti, Juha Plosila, Comparative Study of Synthesis for Asynchronous and Synchronous Cache Controllers. In: Proceedings of the 24th IEEE Norchip Conference, 20-21 November 2006, Linköping, Sweden, 11-14, 2006.

Abstract:

The asynchronous design approach is an interesting
alternative for modern System-On-Chip (SoC) designs because
of its several benefits. Self-timed circuit have potential for lowpower
and low-noise design. Moreover, the modularity and the
composability of asynchronous systems are favorable properties.
This is partly due to the chips getting larger and denser,
resulting in serious difficulties in the clock tree design. One
of disadvantages has been the lack of commercial computer
aided design (CAD) tools. This paper presents synthesis flow
targeted for self-timed VLSI circuits provided by Handshake
Solutions. The performance of the synthesis tool is compared
with its synchronous counterpart in terms of area and speed. We
have chosen to use cache controllers as case study.

BibTeX entry:

@INPROCEEDINGS{inpTuSaPl06a,
  title = {Comparative Study of Synthesis for Asynchronous and Synchronous Cache Controllers},
  booktitle = {Proceedings of the 24th IEEE Norchip Conference, 20-21 November 2006, Linköping, Sweden},
  author = {Tuominen, Johanna and Säntti, Tero and Plosila, Juha},
  pages = {11-14},
  year = {2006},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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