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Formal Power Analysis of On-Chip Communication

Johanna Tuominen, Tomi Westerlund, Juha Plosila, Formal Power Analysis of On-Chip Communication. In: Brasilian Symposium on Formal Methods (SBMF 2007), 87-102, 2007.

Abstract:

We introduce a method to model power consumption of abstract communication
networks for globally asynchronous and locally synchronous systems (GALS)
in Timed Action Systems formalism. The communication network is based on
procedure calls that ensures data integrity during the communication. The
power analysis allows us to estimate the power consumption in a formal,
abstract models, and to steer the development towards power efficient
implementations.

BibTeX entry:

@INPROCEEDINGS{inpTuWePl07a,
  title = {Formal Power Analysis of On-Chip Communication},
  booktitle = {Brasilian Symposium on Formal Methods (SBMF 2007)},
  author = {Tuominen, Johanna and Westerlund, Tomi and Plosila, Juha},
  pages = {87-102},
  year = {2007},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab), Communication Systems (ComSys)

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