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Highly Automated FPGA Synthesis of Application-Specific Protocol Processors

Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius, Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. In: Tero Rissa, Steve Wilton, Philip Leong (Eds.), Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL 2005), 269–274, IEEE Circuits and Systems Society, 2005.

Abstract:

We present a methodology for synthesizing TTA protocol processors onto CMOS and FPGA from application specifications with reduced
designer intervention and a short turn-around time. The methodology builds up on our earlier work in generating synthesizable processor models from system level specifications for 0.18 um CMOS technology. We test the application level methodology by
comparing results obtained from a generated FPGA synthesis model to results obtained from a generated CMOS synthesis model. We
synthesized an architecture for processing the IPv6 protocol, which resulted in an implementation that achieved the clock speed of 45 MHz. Due to the scalable parallelism of TTA architectures, this corresponds to an approximate throughput of 500 Mbps for IPv6
routing. From the results we were able to conclude that the critical delay in our generated FPGA implementations is formed inside our protocol processing functional units.

BibTeX entry:

@INPROCEEDINGS{inpViTrPaIsLi05a,
  title = {Highly Automated FPGA Synthesis of Application-Specific Protocol Processors},
  booktitle = {Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL 2005)},
  author = {Virtanen, Seppo and Truscan, Dragos and Paakkulainen, Jani and Isoaho, Jouni and Lilius, Johan},
  editor = {Rissa, Tero and Wilton, Steve and Leong, Philip},
  publisher = {IEEE Circuits and Systems Society},
  pages = {269–274},
  year = {2005},
}

Belongs to TUCS Research Unit(s): Embedded Systems Laboratory (ESLAB), Communication Systems (ComSys)

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