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Back-Annotation of Timing Information into a Formal Hardware Model: A Case Study

Tomi Westerlund, Jani Paakkulainen, Juha Plosila, Back-Annotation of Timing Information into a Formal Hardware Model: A Case Study. In: Proceedings of IEEE International Symposium on Signals, Circuits & System, ISSCS, 2, IEEE, 2005.

Abstract:

In this paper we present a back-annotation of timing
information into a formal hardware component. The formal
model is represented using Timed Action System with which we
are able to model temporal properties of a system in addition to
functional properties. We give a low-level Timed Action System
model for a protocol processor’s basic components. For these
components we have corresponding synthesisable VHDL models.
The timing information is obtained from the synthesised VHDL
model, and the tenability of the timing is verified against the
given time constraints. Time constraints are used to ensure that
the Timed Action System model fulfils its timing obligations.

BibTeX entry:

@INPROCEEDINGS{inpWePaPl05a,
  title = {Back-Annotation of Timing Information into a Formal Hardware Model: A Case Study},
  booktitle = {Proceedings of IEEE International Symposium on Signals, Circuits & System, ISSCS},
  author = {Westerlund, Tomi and Paakkulainen, Jani and Plosila, Juha},
  volume = {2},
  publisher = {IEEE},
  year = {2005},
}

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