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Time Aware Modelling and Analysis of Multiclocked VLSI Systems

Tomi Westerlund, Juha Plosila, Time Aware Modelling and Analysis of Multiclocked VLSI Systems. In: Zhiming Liu, Jifeng He (Eds.), Formal Methods and Software Engineering, 8th International Conference on Formal Engineering Methods (ICFEM 2006), Lecture Notes in Computer Science 4260, 737–756, Springer Berlin / Heidelberg, 2006.

Abstract:

We introduce a formal, time aware framework for modelling and analysis multiclocked VLSI systems. We define a delay calculus framework for our timed formalism, and, furthermore, constraints with which to confine the
correctness of the system under development, not only logically but also
with respect to timing characteristics. We give an elaborate definition
of the timed formalism, Timed Action Systems, and its delay models. With
the timing aware formal development framework it is possible to obtain
information of multiclocked VLSI systems already at high abstraction levels
as our application, a GALS (globally asynchronous, locally synchronous)
system, shows.

BibTeX entry:

@INPROCEEDINGS{inpWePl06b,
  title = {Time Aware Modelling and Analysis of Multiclocked VLSI Systems},
  booktitle = {Formal Methods and Software Engineering, 8th International Conference on Formal Engineering Methods (ICFEM 2006)},
  author = {Westerlund, Tomi and Plosila, Juha},
  volume = {4260},
  series = {Lecture Notes in Computer Science},
  editor = {Liu, Zhiming and He, Jifeng},
  publisher = {Springer Berlin / Heidelberg},
  pages = {737–756},
  year = {2006},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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