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A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip

Bo Yang, Liang Guang, Tero Säntti, Juha Plosila, A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip. In: Workshop on Designing for Embedded Parallel Computing Platforms in Design Automation and Test Europe Conference (DATE), 26, 2010.

Abstract:

On Network-on-Chip (NoC), dynamic remapping is an effective
technique to recover the processing element (PE) faults while minimiz-
ing the network communication costs. A novel method to transform a
NoC topology into a tree structure and a mapping algorithm based on
the tree model are proposed. The tree structure models the geometri-
cal and spatial relations among the nodes. The algorithm traverses the
tree based on the communication traffic information. It finds a map-
ping solution which replaces the faulty nodes with spare ones using
minimal local migration, and the consequent mapping has minimized
network communication costs. The real-time traffic traces of bench-
mark applications are used to evaluate the efficiency of the proposed
algorithm in terms of run-time of the algorithm and network com-
munication costs. The results show that the run-time is significantly
reduced with lower communication energy and average network delay
compared to existing algorithms. The tree-model based algorithm has
superior run-time features and can be used generically for both static
and dynamic mapping.

BibTeX entry:

@INPROCEEDINGS{inpYaGuSaPl10a,
  title = {A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip},
  booktitle = {Workshop on Designing for Embedded Parallel Computing Platforms in Design Automation and Test Europe Conference (DATE)},
  author = {Yang, Bo and Guang, Liang and Säntti, Tero and Plosila, Juha},
  pages = {26},
  year = {2010},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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