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Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip

Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila, Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip. In: 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS),, 2010.

Abstract:

With the NoC size growing constantly, efficient
algorithms are needed to provide power/performance-aware task
mapping on massively parallel systems. In this paper a novel tree-
model based mapping algorithm is proposed, to achieve high
energy efficiency and low latency on NoC platforms. A NoC
is abstracted as a tree composed of a root node and median
nodes at different levels. By mapping tasks starting from the
root of the tree, our algorithm minimizes the communication
cost and consequently reduces the energy consumption and
network delay. Experimental results show that the run-time of
our algorithm is decreased by 90% on average compared to the
Greedy Incremental (GI) algorithm. Full system simulation also
shows that for Radix traffic, compared to the original random
mapping, the GI achieves 18.7% and 17.3% reduction in energy
consumption and average network latency respectively, while our
algorithm achieves 24.7% and 40.8% reduction respectively.

BibTeX entry:

@INPROCEEDINGS{inpYaXuSaPl10a,
  title = {Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip},
  booktitle = { 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS),},
  author = {Yang, Bo and Xu, Thomas Canhao and Säntti, Tero and Plosila, Juha},
  year = {2010},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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