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Design of the Processing Core of a Mixed-Signal CMOS DTCNN Chip for Pixel-Level Snakes

Victor M. Brea, David L. Vilarino, Ari Paasio, Diego Cabello, Design of the Processing Core of a Mixed-Signal CMOS DTCNN Chip for Pixel-Level Snakes. Transactions on Circuits and Systems - I 51(5), 997-1013, 2004.

Abstract:

This paper introduces the processing core of a full-custom
mixed-signal CMOS chip intended for an active-contour-based
technique, the so-called pixel-level snakes (PLS). Among the
different parameters to optimize on the top-down design flow our
methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and
processing element. This is the first prototype for PLS; an integrated
circuit with a 9 9 resolution manufactured in a 0.25 - um CMOS STMicroelectronics technology process. Awaiting for experimental
results, HSPICE simulations prove the validity of the approach
introduced here.

BibTeX entry:

@ARTICLE{jBrViPaCa04a,
  title = {Design of the Processing Core of a Mixed-Signal CMOS DTCNN Chip for Pixel-Level Snakes},
  author = {Brea, Victor M. and Vilarino, David L. and Paasio, Ari and Cabello, Diego},
  journal = {Transactions on Circuits and Systems - I},
  volume = {51},
  number = {5},
  pages = {997-1013},
  year = {2004},
  keywords = {Active contours, application-specific integrated  circuit (ASIC), cellular neural network (CNN), CNN robustness,discrete-time CNN (DTCNN), mixed-signal design, pixel-level snakes (PLS)},
}

Belongs to TUCS Research Unit(s): Microelectronics

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