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Bi-LCQ: A Low-Weight Clustering-Based Q-Learning Approach for NoCs

Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Plosila Plosila, Bi-LCQ: A Low-Weight Clustering-Based Q-Learning Approach for NoCs. Microprocessors and Microsystems 38(1), 64–75, 2014.

Abstract:

Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.

BibTeX entry:

@ARTICLE{jFaEbDaLiPl14a,
  title = {Bi-LCQ: A Low-Weight Clustering-Based Q-Learning Approach for NoCs},
  author = {Farahnakian, Fahimeh and Ebrahimi, Masoumeh and Daneshtalab, Masoud and Liljeberg, Pasi and Plosila, Plosila},
  journal = {Microprocessors and Microsystems},
  volume = {38},
  number = {1},
  publisher = {Elsevier},
  pages = {64–75},
  year = {2014},
  keywords = {Network-on-Chip; Congestion-aware routing algorithm; Adaptive routing algorithm; Q-learning and Q-routing approaches},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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