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TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Muhammad Ali, Plosila Juha, Publication date, 2015/5/23, Journal, Microprocessors, Microsystems, Publisher, Elsevier, Description, Abstract Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling, CDMA platforms to meet the high performance demanded by modern applications (eg 4G, etc.). Recently proposed CGRAs offer time-multiplexing, dynamic applications, parallelism to enhance device utilization, reduce energy consumption at the cost of, additional memory (up to 50% area of the overall platform). To reduce the memory, novel CGRAs employ either statistical compression intermediate compact ... overheads, TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. Microprocessors and Microsystems , 1–14, 2015.

http://dx.doi.org/10.1016/j.micpro.2015.05.002

Abstract:

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

BibTeX entry:

@ARTICLE{jJaDaHeAlPlPu20JoMiMiPuElDeAbpletdypareadov15a,
  title = {TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs},
  author = {Jafri, Syed M. A. H. and Daneshtalab, Masoud and Hemani, Ahmed and Ali, Muhammad and Plosila Juha and Publication date and 2015/5/23 and Journal and Microprocessors and Microsystems and Publisher and Elsevier and Description and Abstract Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling and platforms to meet the high performance demanded by modern applications (eg 4G, CDMA and etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications and parallelism to enhance device utilization and reduce energy consumption at the cost of and additional memory (up to 50% area of the overall platform). To reduce the memory and overheads, novel CGRAs employ either statistical compression intermediate compact ...},
  journal = {Microprocessors and Microsystems},
  publisher = {Elsevier},
  pages = {1–14},
  year = {2015},
  ISSN = {1872-9436},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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