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Design of the Coarse-Grained Reconfigurable Architecture DART with On-Line Error Detection

Syed M. A. H. Jafri, Stanislaw Piestrak, Oliver Sentieys, Sabestian Pillement, Design of the Coarse-Grained Reconfigurable Architecture DART with On-Line Error Detection. Microprocessors and Microsystems 1, 1–14, 2014.

http://dx.doi.org/10.1016/j.micpro.2013.12.004.

Abstract:

This paper presents the implementation of the coarse-grained reconfigurable architecture (CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison. These low-cost hardware techniques would allow to tolerate temporary faults (including so called soft errors caused by radiation), provided that some technique based on re-execution of the last operation is used. Synthesis results obtained for a 90 nm CMOS technology have confirmed significant hardware and power consumption savings of the proposed approach over commonly used duplication with comparison. Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design.

BibTeX entry:

@ARTICLE{jJaPiSePi14a,
  title = {Design of the Coarse-Grained Reconfigurable Architecture DART with On-Line Error Detection},
  author = {Jafri, Syed M. A. H. and Piestrak, Stanislaw and Sentieys, Oliver and Pillement, Sabestian},
  journal = {Microprocessors and Microsystems},
  volume = {1},
  publisher = {Elsevier},
  pages = {1–14},
  year = {2014},
  keywords = {Coarse-grained reconfigurable architectures, Fault-tolerance, Online fault detection, residue mod 3},
}

Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)

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