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A Mixed-Mode Polynomial Cellular Array Processor Hardware Realization

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen, A Mixed-Mode Polynomial Cellular Array Processor Hardware Realization. IEEE Transactions on Circuits and Systems I: Regular Papers 51(2), 286-297, 2004.

Abstract:

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm^2, 1.027 million transistor cellular array processor with 2 X 72 PUs and 36 layers of memory in each was manufactured using a 0.25-um digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72 X 72 data while keeping all input–output operations during processing local. One complete Heun's iteration round takes 166.4us and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.

BibTeX entry:

@ARTICLE{jLaPaKaHa04a,
  title = {A Mixed-Mode Polynomial Cellular Array Processor Hardware Realization},
  author = {Laiho, Mika and Paasio, Ari and Kananen, Asko and Halonen, Kari},
  journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
  volume = {51},
  number = {2},
  pages = {286-297},
  year = {2004},
}

Belongs to TUCS Research Unit(s): Microelectronics

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