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Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Teijo Lehtonen, David Wolpert, Pasi Liljeberg, Juha Plosila, Paul Ampadu, Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(4), 527–540, 2010.

Abstract:

We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose–Chaudhuri–Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.

BibTeX entry:

@ARTICLE{jLeWoLiPlAm10a,
  title = {Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects},
  author = {Lehtonen, Teijo and Wolpert, David and Liljeberg, Pasi and Plosila, Juha and Ampadu, Paul},
  journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  volume = {18},
  number = {4},
  pages = {527–540},
  year = {2010},
  keywords = {Adaptive systems, digital systems, fault tolerance, forward error correction (FEC), integrated circuit interconnections, networks-on-chip (NoCs), reliability, self-testing},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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