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Dynamic Power Reduction of Stalls in Pipeline Architecture Processors

Pejman Lotfi-kamran, Ali-asghar Salehpour, Amir-mohammad Rahmani, Ali Afzali-kusha, Zainalabedin Navabi, Dynamic Power Reduction of Stalls in Pipeline Architecture Processors. International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS) 1(1), 9-15, 2011.

Abstract:

This paper proposes a technique for dynamic power reduction of pipelined processors. It is based on eliminating unnecessary transitions that are generated during the execution of NOP instructions. The approach includes the elimination of unnecessary changes in pipe register contents and the limitation of boundary movement of transitions caused by inevitable changes in pipe register contents due to insertion of a NOP into a pipelined processor. To assess its efficiency, the proposed technique is applied to MIPS, DLX, and PAYEH processors considering a number of benchmarks. The experimental results show that the techniques can lead to up to 10% reduction in the dynamic power consumption at a cost of negligible (almost zero) speed and (about 0.2%) area overheads

BibTeX entry:

@ARTICLE{jLoSaRaAfNa11a,
  title = {Dynamic Power Reduction of Stalls in Pipeline Architecture Processors},
  author = {Lotfi-kamran, Pejman and Salehpour, Ali-asghar and Rahmani, Amir-mohammad and Afzali-kusha, Ali and Navabi, Zainalabedin},
  journal = {International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS)},
  volume = {1},
  number = {1},
  pages = {9-15},
  year = {2011},
  keywords = {Dataflow architectures, low-power design, pipelined processors, stall},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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