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A Differential Architecture for an Online Analog Viterbi Decoder

Janne Maunu, Mika Laiho, Ari Paasio, A Differential Architecture for an Online Analog Viterbi Decoder. IEEE Transactions on Circuits and Systems - I 55, 1133-1140, 2008.

Abstract:

A differential architecture of an analog Viterbi decoder is presented. Analog processing enables the analog-digital converter to be excluded from the decoder realization. Moreover, high-speed operation can be achieved via differential processing. We describe the differential operation, together with the resulting decoder structure. The differential architecture enables the trace-back memory to be excluded and makes online decoding after initial transitional stages possible. We analyze the performance of the differential analog decoder by including analog circuit nonidealities in the system-level model. The decoder obeys a nonlinear transfer function, and the monotonical growth of path metrics is avoided by scaling and subtraction of the global minimum. The resulting differential analog decoder performance is compared with the performance of a 3-bit soft-decision digital Viterbi decoder. The simulations are performed for a (2,1,7) convolutional code.

BibTeX entry:

@ARTICLE{jMaLaPa08a,
  title = {A Differential Architecture for an Online Analog Viterbi Decoder},
  author = {Maunu, Janne and Laiho, Mika and Paasio, Ari},
  journal = {IEEE Transactions on Circuits and Systems - I},
  volume = {55},
  pages = {1133-1140},
  year = {2008},
  keywords = {analog systems, differential geometry, forward error correction (FEC), parallel architectures},
}

Belongs to TUCS Research Unit(s): Microelectronics

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