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An Analog 2D DCT Processor

Mikko Pänkäälä, Kati Virtanen, Ari Paasio, An Analog 2D DCT Processor. IEEE Transactions on Circuits and Systems for Video Technology 16(10), 1209–1216, 2006.

Abstract:

This paper presents a simple and low-cost analog
architecture for computing 2-dimensional discrete cosine transform
(2-D DCT). The proposed circuit is aimed for low-power
or very high-speed moderate image quality video compression
applications. The design uses current-mode signaling and has two
separate 1-D DCT kernels, thus no memory is needed for storing
intermediate results. Moreover, the circuit works in continuous
time. Simple current mirrors have been used to realize all the
needed matrix operations and the transistors are dimensioned in
such a way that current level of 20 μA is not exceeded to ensure
low-power operation. A prototype chip which includes both 4-
point and 8-point forward transforms has been fabricated in a
0.18 μm digital CMOS technology. The operation of the circuit
is analyzed with help of measurement results obtained from test
chips.

BibTeX entry:

@ARTICLE{jPaViPa06a,
  title = {An Analog 2D DCT Processor},
  author = {Pänkäälä, Mikko and Virtanen, Kati and Paasio, Ari},
  journal = {IEEE Transactions on Circuits and Systems for Video Technology},
  volume = {16},
  number = {10},
  pages = {1209–1216},
  year = {2006},
  keywords = {Discrete cosine transform, image coding},
}

Belongs to TUCS Research Unit(s): Microelectronics

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