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A Ranked Order Filter Implementation for Parallel Analog Processing

Jonne Poikonen, Ari Paasio, A Ranked Order Filter Implementation for Parallel Analog Processing. IEEE Transactions on Circuits and Systems - I 51, 974-987, 2004.

Abstract:

Order statistic filtering, the generalization of which
is ranked order filtering, is needed for many image-processing
functions including median filtering and mathematical morphology.
Combining order statistic functionality with the parallel
operation and local connectivity of array processing approaches
such as the cellular nonlinear network model, has the potential
for very high performance in image processing. This paper
examines the implementation of programmable ranked order
extraction with a very compact hardware realization of an analog
current-mode ranked order filter. The considerable savings in the
required circuit area, compared to other circuits, make it possible
to use the structure as a building block in a massively parallel
signal processing array. The operation of the circuit is analyzed
in detail with the help of simulations and measurement results
obtained from a test chip manufactured in a 0.18-um standard
digital CMOS technology are also presented. The simulations and
measurement results verify the correct operation of the circuit and
show that it is very suitable for inclusion in every cell of a large
parallel processor array. This makes many grayscale processing
functions available with truly parallel operation and therefore
very high performance.

BibTeX entry:

@ARTICLE{jPoPa04a,
  title = {A Ranked Order Filter Implementation for Parallel Analog Processing},
  author = {Poikonen, Jonne and Paasio, Ari},
  journal = {IEEE Transactions on Circuits and Systems - I},
  volume = {51},
  pages = {974-987},
  year = {2004},
  keywords = {Analog array processing, order statistic filtering, ranked order filter},
}

Belongs to TUCS Research Unit(s): Microelectronics

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