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Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen, Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(6), 766–770, 2008.

Abstract:

In this paper, an analytical model for the current draw of an on-chip bus
is presented. The model is combined with an on-chip power supply grid model
in order to analyze noise caused by switching buses in a power supply grid.
The bus is modeled as distributed resistance-inductance-capacitance (RLC)
lines that are capacitively and inductively coupled to each other.
Different switching patterns and driver skewing times are also included
in the model. The power supply grid is modeled as a network of RLC
segments. The model is verified by comparing it to HSPICE. The error was
below 8%. The model is applied to determine the influence of driver
skewing times on maximum power supply noise.

BibTeX entry:

@ARTICLE{jTuZhIsTe08a,
  title = {Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid},
  author = {Tuuna, Sampo and Zheng, Li-Rong and Isoaho, Jouni and Tenhunen, Hannu},
  journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  volume = {16},
  number = {6},
  pages = {766–770},
  year = {2008},
  keywords = {Bus, power supply noise, transmission line},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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