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A Study of 3D Network-on-Chip Design for Data Parallel H.264 Coding

Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen, A Study of 3D Network-on-Chip Design for Data Parallel H.264 Coding. Microprocessors and Microsystems 35(7), 603–612, 2011.

Abstract:

In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 2D design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.

BibTeX entry:

@ARTICLE{jXuYiLiTe11a,
  title = {A Study of 3D Network-on-Chip Design for Data Parallel H.264 Coding},
  author = {Xu, Thomas Canhao and Yin, Alexander Wei and Liljeberg, Pasi and Tenhunen, Hannu},
  journal = {Microprocessors and Microsystems},
  volume = {35},
  number = {7},
  publisher = {Elsevier},
  pages = {603–612},
  year = {2011},
  keywords = {N/A},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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