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An Analysis of Designing 2D/3D Chip Multiprocessor with Different Cache Architecture

Thomas Canhao Xu, Liang Guang, Alexander Wei Yin, Bo Yang, Pasi Liljeberg, Hannu Tenhunen, An Analysis of Designing 2D/3D Chip Multiprocessor with Different Cache Architecture. In: 28th IEEE Norchip Conference, 1-6, IEEE, 2010.

BibTeX entry:

@INPROCEEDINGS{pXuLiTe10k,
  title = {An Analysis of Designing 2D/3D Chip Multiprocessor with Different Cache Architecture},
  booktitle = {28th IEEE Norchip Conference},
  author = {Xu, Thomas Canhao and Guang, Liang and Yin, Alexander Wei and Yang, Bo and Liljeberg, Pasi and Tenhunen, Hannu},
  publisher = {IEEE},
  pages = {1-6},
  year = {2010},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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