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FANSI: Fault Tolerant Network-on-Chip Simulator

Teijo Lehtonen, Ville Rantala, Pasi Liljeberg, Juha Plosila, FANSI: Fault Tolerant Network-on-Chip Simulator. TUCS Technical Reports 935, Turku Centre for Computer Science, 2009.

Abstract:

This report presents a simulator for simulating fault tolerance issues on Network-on-
Chip (NoC) architectures. The simulator is called FANSI which stands for fault tolerant Network-on-Chip simulator. The simulator models the basic building blocks of a Network-on-Chip including a router, a link and a network interface. To simulate the NoC there are also models for a basic computational core and a packet to be transferred in network. Different NoC topologies and routing algorithms can be analyzed with the simulator. The simulator also provides features for modelling faults in the NoC and therefore makes it possible to analyze fault tolerance of NoC architectures.
The report presents two topologies, mesh and tree, and routing algorithms for them. The report includes also a simulation example demonstrating the usage of the simulator and its reporting features. The source codes for the header files are provided in the report.

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BibTeX entry:

@TECHREPORT{tLeRaLiPl09a,
  title = {FANSI: Fault Tolerant Network-on-Chip Simulator},
  author = {Lehtonen, Teijo and Rantala, Ville and Liljeberg, Pasi and Plosila, Juha},
  number = {935},
  series = {TUCS Technical Reports},
  publisher = {Turku Centre for Computer Science},
  year = {2009},
  keywords = {Network-on-Chip, simulator, fault tolerance},
  ISBN = {978-952-12-2272-6},
}

Belongs to TUCS Research Unit(s): Distributed Systems Laboratory (DS Lab)

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