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Fault-Tolerant Routing Approach for Reconfigurable Networks-on-chip

Pekka Rantala, Teijo Lehtonen, Jouni Isoaho, Juha Plosila, Fault-Tolerant Routing Approach for Reconfigurable Networks-on-chip. In: Proceedings of the International Symposium on System-on-Chip (SoC) 2006, Tampere, Finland, November 13-16, 2006, 2006.

Abstract:

We introduce fault-tolerant on-chip routing philosophy
for two-dimensional meshes. It is an extension to the
concept of packet connected circuit, PCC. In order to increase
reliability we have designed an automatic rerouting property
to a single switch node and added return channel to the
communication route. An autonomic routing switch node is
modeled asynchronously and implemented using Haste language.
The logical functionality of routing is illustrated as a single study
case in 7*8 mesh. The routing success is further analyzed in
congesting and faulty environment.

Files:

Abstract in PDF-format

BibTeX entry:

@INPROCEEDINGS{inpRaLeIsPl06a,
  title = {Fault-Tolerant Routing Approach for Reconfigurable Networks-on-chip},
  booktitle = {Proceedings of the International Symposium on System-on-Chip (SoC) 2006, Tampere, Finland, November 13-16, 2006},
  author = {Rantala, Pekka and Lehtonen, Teijo and Isoaho, Jouni and Plosila, Juha},
  year = {2006},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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