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Modified SRCMOS Cell for High-Throughput Wave-Pipelined Arithmetic Units

Tero Säntti, Jouni Isoaho, Modified SRCMOS Cell for High-Throughput Wave-Pipelined Arithmetic Units. In: Proceedings of the IEEE International Symposium on Circuit and Systems, ISCAS, 2001.

Abstract:

In this paper a modified basic cell for wave-pipelines is proposed. The cell is self resetting and has complementary outputs. Simulations of the cell demonstrate that delay variations for all input combinations are small, and the cell's sensitivity to pulse length variation is reduced. 8x8 and 16x16 -bit multipliers are designed using 0.35$\mu$m 2.5V CMOS technology. The proposed units display a cycle time of 620 ps, corresponding to maximum operation frequency of 1.6 GHz.

Files:

Abstract in PDF-format

BibTeX entry:

@INPROCEEDINGS{inpSaIs01a,
  title = {Modified SRCMOS Cell for High-Throughput Wave-Pipelined Arithmetic Units},
  booktitle = {Proceedings of the IEEE International Symposium on Circuit and Systems, ISCAS},
  author = {Säntti, Tero and Isoaho, Jouni},
  year = {2001},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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