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Formal Specification of an Asynchronous Viterbi Decoder

Johanna Tuominen, Juha Plosila, Formal Specification of an Asynchronous Viterbi Decoder. In: Proceedings of 23rd Norchip Conference, 214-217, 2005.

Abstract:

Conventionally, the correctness of functional and non-functional
properties of hardware components is ensured during design process
by simulation. Moreover, different description languages are needed
during development phases. Thus, by adopting the Action Systems, we
are able to use the same formalism from specification down to
implementation. Recently, we have been exploiting possibilities to
formally model power consumption. That is the purpose is to develop
a formal power estimation flow which can be used to monitor the
power consumption from abstract level down to the gate level
implementation. In this paper, we present a formal model for
asynchronous Viterbi decoder, which will be used as a case study for
the power estimation flow in the future.

Files:

Abstract in PDF-format

BibTeX entry:

@INPROCEEDINGS{inpTuPl05a,
  title = {Formal Specification of an Asynchronous Viterbi Decoder},
  booktitle = {Proceedings of 23rd Norchip Conference},
  author = {Tuominen, Johanna and Plosila, Juha},
  pages = {214-217},
  year = {2005},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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