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NoC Interface for a Protocol Processor

Seppo Virtanen, Jani Paakkulainen, Tero Nurmi, Jouni Isoaho, NoC Interface for a Protocol Processor. In: Proceedings of the 21st IEEE NORCHIP Conference, 31-34, 2003.

Abstract:

In this paper we present our design and implementation of
Network-on-Chip (NoC) support into our TACO protocol processor
architecture. Our signaling scheme is Virtual Component Interface
standard (VCI) compliant. Due to the data- and I/O-intensive nature
of protocol processing, memory access from I/O logic plays a key
role in NoC interface design. We have addressed this problem by
using dual-port memory for protocol data units (PDUs) and a separate
single port memory for other user data. We evaluated our NoC
interface with VHDL synthesis of a case study in IPv6 processing.
Based on our simulations and synthesis, the logic part is able to
operate at 200 MHz in 0.18 $\mu$m CMOS technology. Adding a NoC
interface into our architecture did not considerably increase area
and power costs.

Files:

Abstract in PDF-format

BibTeX entry:

@INPROCEEDINGS{inpViPaNuIs03a,
  title = {NoC Interface for a Protocol Processor},
  booktitle = {Proceedings of the 21st IEEE NORCHIP Conference},
  author = {Virtanen, Seppo and Paakkulainen, Jani and Nurmi, Tero and Isoaho, Jouni},
  pages = {31-34},
  year = {2003},
}

Belongs to TUCS Research Unit(s): Embedded Systems Laboratory (ESLAB), Microelectronics, Communication Systems (ComSys)

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