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From UML Behavioral Descriptions to Efficient Synthesizable VHDL

Dag Björklund, Johan Lilius, From UML Behavioral Descriptions to Efficient Synthesizable VHDL. In: Proceedings of the 20th IEEE Norchip Conference, 2002.

Abstract:

Different approaches to high-level synthesis are currently being studied for different specification language - target language pairs. In the paper we describe a strategy for high-level synthesis that can be used for code generation from several specification languages into several target languages. We demonstrate the approach using VHDL synthesis from UML behavioral models as an example. The UML models are first translated into textual code in a language called SMDL. SMDL is a high level language for multiple models of computation that can be compiled into efficient target language code e.g. VHDL.

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BibTeX entry:

@INPROCEEDINGS{pBjLi02c,
  title = {From UML Behavioral Descriptions to Efficient Synthesizable VHDL},
  booktitle = {Proceedings of the 20th IEEE Norchip Conference},
  author = {Björklund, Dag and Lilius, Johan},
  year = {2002},
}

Belongs to TUCS Research Unit(s): Embedded Systems Laboratory (ESLAB)

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