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A Framework for Rapid Design and Evaluation of Protocol Processors

Seppo Virtanen, A Framework for Rapid Design and Evaluation of Protocol Processors. TUCS Dissertations 55. Turku Centre for Computer Science, 2004.

Abstract:

Network hardware design is becoming increasingly challenging as more and more demands are put on network bandwidth and throughput requirements. A potential solution to this is designing programmable processors with network-optimized hardware. The challenge in designing such programmable network or protocol processors is to find an architecture that is as good a compromise as possible between a general purpose processor and an ASIC implementation. An ideal protocol processor would harness both the programmability of general purpose processors and the application-specific hardware optimization of ASICs. Looking at current products and solutions, it can be observed that there is a continuing need to better understand the exact needs of protocol processing in terms of designing and implementing both hardware and software architectures. Thus, in addition to developing new architectures with optimized processing elements, attention must also be paid to application-domain-specific processor design methodologies for protocol processing.
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In this PhD thesis a transport triggered (TTA) hardware platform and a system design methodology for protocol processing are presented. The methodology supports rapid and accurate prototyping with inexpensive computers at the system level, and reliable synthesis model generation and logic synthesis after the system level prototyping. Component reuse and design space exploration capabilities are also vital parts of the methodology. The library-based hardware platform is optimized for protocol processing and has native processing elements for vital protocol processing functions like e.g. checksum calculations. The hardware platform presented in this thesis is the first optimized application of the TTA paradigm to protocol processing. The design methodology presents novel EDA techniques as well as improvements to existing EDA technologies. These include e.g. system modeling at heterogeneous abstraction levels and the use of object oriented techniques in system level prototyping. The capabilities of the hardware platform and the design methodology are verified with three protocol processing case studies.
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This PhD thesis is a monograph of 185 pages.

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BibTeX entry:

@PHDTHESIS{phdVirtanen04a,
  title = {A Framework for Rapid Design and Evaluation of Protocol Processors},
  author = {Virtanen, Seppo},
  number = {55},
  series = {TUCS Dissertations},
  school = {Turku Centre for Computer Science},
  year = {2004},
  keywords = {protocol processor, system level design, SystemC, hardware/software codesign},
  ISBN = {952-12-1410-4},
}

Belongs to TUCS Research Unit(s): Embedded Systems Laboratory (ESLAB), Communication Systems (ComSys)

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