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Feasibility Report on Asynchronous Synthesis

Johanna Tuominen, Tero Säntti, Juha Plosila, Feasibility Report on Asynchronous Synthesis. TUCS Technical Reports 765, Turku Centre for Computer Science, 2006.

Abstract:

The asynchronous design approach is an interesting alternative to the commonly used synchronous approach because of its several benefits. Self-timed circuit have potential for low-power and low-noise design. Moreover, the modularity and the composability of asynchronous systems are favorable properties. This is partly due to the chips getting larger and denser, resulting in serious difficulties in the clock tree design. One of disadvantages has been the lack of commercial computer aided design (CAD) tools. This paper presents synthesis flow targeted for selftimed
VLSI circuits provided by Handshake Solutions. The performance of the
synthesis tool is compared with its synchronous counterpart in terms of area and speed. We have chosen to use cache controllers as case study.

Files:

Full publication in PDF-format

BibTeX entry:

@TECHREPORT{tTuSaPl06a,
  title = {Feasibility Report on Asynchronous Synthesis},
  author = {Tuominen, Johanna and Säntti, Tero and Plosila, Juha},
  number = {765},
  series = {TUCS Technical Reports},
  publisher = {Turku Centre for Computer Science},
  year = {2006},
  keywords = {Asynchronous, Synthesis, Haste, Power Consumption},
  ISBN = {952-12-1717-0},
}

Belongs to TUCS Research Unit(s): Communication Systems (ComSys)

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